1. Field of the Invention
The present invention relates to a semiconductor amplifier comprising, for example, field-effect transistors or bipolar transistors for high frequency amplification, and relates more specifically to a high efficiency amplifier used, for example, in mobile communications devices and microwave band communications devices.
2. Description of the Related Art
B-class amplifiers are commonly used for high frequency power amplifiers in mobile communications devices and microwave band communications devices.
A typical B-class amplifier circuit according to the related art is shown in FIG. 26. As shown in FIG. 26, the source of field-effect transistor (FET) 201 in this amplifier is grounded. A drain bias voltage is applied to the drain of FET 201 via a drain bias line 204 from a drain bias power supply terminal 203, and a capacitor 202 is inserted between the ground and drain bias power supply terminal 203. A high frequency signal to be amplified is input to the gate of FET 201 from a signal input terminal 205. The signal amplified by FET 201 is output through a fundamental wave matching circuit 206 from a signal output terminal 207. In this B-class amplifier, the gate bias point of the FET 201 is set so that the dc drain current goes to zero.
FIG. 27 is a graph showing the waveforms of the drain current and drain voltage in the FET 201 shown in FIG. 26. The drain voltage is indicated by a solid line in FIG. 27, and the drain current is indicated by a dotted line. Note that the drain voltage has a sine wave shaped waveform, and the drain current has a half-wave rectified waveform. Note, further, that the shaded area indicates power loss.
As will be known from FIG. 27, a problem with an amplifier as shown in FIG. 26 is that power loss occurs, and efficiency therefore drops, when the drain current is greater than zero and the drain voltage is also greater than zero.
It should be further noted that high harmonic processing wherein even harmonics are short circuited and odd harmonics are open circuited is taught in Japanese Patent Laid-Open Publication Nos.7-94974, 8-130424, and 9-246889.
An FET mixer comprising a low pass filter connected between an FET and IF band matching circuit is also taught in Japanese Patent Laid-Open Publication No.2-94908.